Conventionally, the constitution shown in FIG. 8 is known as an example of an A/D (analog/digital) conversion circuit (for example, refer to Non-patent Document 1). FIG. 8 is a diagram showing the configuration of the conventionally known A/D conversion circuit.
In the example shown, the A/D conversion circuit 190 includes a clock generating circuit 191 that couples in a ring shape one negative AND (NAND) circuit 1911 as an inverting circuit for activation that operates upon receiving a pulse signal StartP to one input terminal, and a plurality of inverter (INV) circuits 1912 as inverting circuits; a counter 192 and an encoder 193 that measure the output signal from the clock generating circuit 191; a latch circuit 194 that holds the output signal from the counter 192; a latch circuit 195 that holds the output signal from the encoder 193; a latch circuit 196 that adds the output signals from the latch circuit 194 and the latch circuit 195 and holds the sum; and a computing unit 197 that computes the difference between the previous signal and the current signal using the latch circuit 196, and outputs it to an external subsequent stage circuit.
Also, in the illustrated example, the NAND circuit 1911 and the inverter circuits 1912 in the clock generating circuit 191, and a power source line 1913 for supplying power to the inverter circuits 1912 are connected to an input terminal 198 of the analog input signal Vin that is the object of the A/D conversion via a buffer circuit 199. Also, clock (CLK) signal CKs is input to the encoder 193 and the latch circuits 194 and 195.
Next, the operation of the A/D conversion circuit 190 shall be described. As shown in FIG. 8, the clock generating circuit 191 causes the pulse signal StartP to go around the circuit consisting of the single NAND circuit 1911 and the plurality of inverter circuits 1912 that are configured in a ring shape.
The counter 192 counts the number of times that the pulse signal StartP, which changes in accordance with the analog input signal Vin and the cycle of the clock (CLK) signal CKs, goes around the circuit in the clock generating circuit 191, and outputs it as binary digital data. The encoder 193 detects the position of the pulse signal StartP, which changes in accordance with the analog input signal Vin and the cycle of the clock (CLK) signal CKs, in the loop of the circuit in the clock generating circuit 191, and outputs it as binary digital data.
The latch circuit 194 holds the digital data that counter 192 outputs. The latch circuit 195 holds the digital data that the encoder 193 outputs. The latch circuit 196 makes the digital data that the latch circuit 194 holds the high-order bits, and the digital data that the latch circuit 195 holds the low-order bits and takes them in, and by adding together these digital data, generates and holds binary digital data according to the analog input signal Vin in the cycle of the clock signal CKs.
The computing unit 197 computes the difference between the digital data that the latch circuit 196 held with the previous digital data that the latch circuit 196 held, and outputs the computed digital data DT to an external subsequent stage circuit.
FIG. 9 is a diagram that shows the relation between the magnitude of the analog input signal Vin in the A/D conversion circuit 190, and the propagation delay time of the pulse signal StartP that travels in the circuit. In the A/D conversion circuit 190, in the case of the analog input signal Vin being low, the propagation delay time of the pulse signal StartP increases, and in the case of the analog input signal Vin being high, the propagation delay time of the pulse signal StartP decreases. Accordingly, digital data according to the propagation delay time of this pulse signal StartP is output from the A/D conversion circuit 190.
FIG. 10 is a diagram that shows the relation of the sampling cycle in the A/D conversion circuit 190 and the timing of outputting digital data. The A/D conversion circuit 190 cyclically outputs the digital data DT in accordance with the cycle of the clock signal CKs that is the sampling cycle. In the example that is illustrated, it outputs the digital data 2121 at the sampling cycle 2111, outputs the digital data 2122 at the sampling cycle 2112, and outputs the digital data 2123 at the sampling cycle 2113.
As stated above, the A/D conversion circuit 190 cyclically outputs the digital data DT corresponding to the analog input signal Vin in accordance with the cycle of the clock signal CKs.
Also, as a clock generating circuit that is included in an A/D conversion circuit, there is known a constitution that provides a delay element between inverting circuits that constitute the clock generating circuit (for example, refer to Patent Document 1). According to this constitution, compared to the case of there being no delay element, by delaying the propagation speed of the clock signal of the clock generating circuit, a reduction in malfunctioning becomes possible by hindering the effects of wiring resistance, wiring capacity and parasitic elements.